1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that allows a proper check while it is on a wafer.
2. Description of the Related Art
WLBI (wafer level burn-in) is a process of stabilizing characteristics of semiconductor devices by exposing them to a high temperature and high voltage environment for a predetermined time period.
In the WLBI of DRAMs, a high voltage is applied to predetermined circuitry inside the memory chip, and chips are rejected if they have cell transistors with insufficient static charge tolerance. In detail, a mode flag signal indicative of the WLBI test is input to the chip, thereby entering in the WLBI test mode. In the WLBI test mode, bit lines are fixed to the ground level (i.e., the voltage level of the ground-side power supply voltage), and word lines are all selected and placed in the activated state. With the bit lines clamped to the low voltage level, a high gate voltage is applied to all the cell transistors in this manner to place them under stress.
If the static charge tolerance of cell transistors is insufficient, they will be destroyed during the test. Chips having broken transistors can be easily identified by checking the chips"" electric power consumption, thereby rejecting the chips with destroyed transistors.
The WLBI test as described above can reject chips only if these chips have insufficient static charge tolerance. In reality, insufficient static charge tolerance surfaces as a problem even between adjacent bit lines or adjacent storage points (i.e., joint points between a memory cell and a cell transistor). It is thus desirable to test such static charge tolerance.
Accordingly, there is a need for a semiconductor memory device that allows testing of various static charge tolerances in the WLBI test.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor memory device according to the present invention includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
In the semiconductor memory device described above, a clamp-voltage generation circuit is provided to supply the first clamp voltage to the first sense amplifier circuits and to supply the second clamp voltage to the second sense amplifier circuits in the test mode. With this configuration, during test operation, the odd-number bit lines are clamped to the first clamp voltage, and the even-number bit lines are clamped to the second clamp voltage. Accordingly, a voltage difference is generated between bit lines to apply a stress, thereby making it possible to test static-charge tolerance between the bit lines.
Further, selection of all word lines, if so selected, makes it possible to test static-charge tolerance between storage points.
Moreover, the first and second clamp voltages may be set to voltages varying depending on a code signal supplied from an exterior of the semiconductor memory device. This makes it possible to clamp all the bit lines to LOW, thereby conducting a conventional static-charge tolerance test.